mchp_clock_pic32ck_sg_gc.h File Reference

Clock control header file for Microchip pic32ck_sg_gc family. More...

#include <zephyr/dt-bindings/clock/mchp_pic32ck_sg_gc_clock.h>

Go to the source code of this file.

Data Structures
struct	clock_mchp_subsys_xosc_config
	External Crystal Oscillator configuration structure. More...
struct	clock_mchp_subsys_dfll48m_config
	DFLL 48MHz configuration structure. More...
struct	clock_mchp_subsys_pll_config
struct	clock_mchp_subsys_pll_out_config
struct	clock_mchp_subsys_rtc_config
	RTC configuration structure. More...
struct	clock_mchp_subsys_xosc32k_config
	External 32.768 kHz crystal oscillator configuration structure. More...
struct	clock_mchp_subsys_gclkgen_config
	Gclk Generator configuration structure. More...
struct	clock_mchp_subsys_gclkperiph_config
	Gclk Peripheral configuration structure. More...
struct	clock_mchp_subsys_mclkcpu_config
	MCLK configuration structure. More...

Typedefs
typedef uint32_t *	clock_mchp_rate_t
	clock rate datatype

Enumerations
enum	clock_mchp_gclkgen {   CLOCK_MCHP_GCLKGEN_GEN0 , CLOCK_MCHP_GCLKGEN_GEN1 , CLOCK_MCHP_GCLKGEN_GEN2 , CLOCK_MCHP_GCLKGEN_GEN3 ,   CLOCK_MCHP_GCLKGEN_GEN4 , CLOCK_MCHP_GCLKGEN_GEN5 , CLOCK_MCHP_GCLKGEN_GEN6 , CLOCK_MCHP_GCLKGEN_GEN7 ,   CLOCK_MCHP_GCLKGEN_GEN8 , CLOCK_MCHP_GCLKGEN_GEN9 , CLOCK_MCHP_GCLKGEN_GEN10 , CLOCK_MCHP_GCLKGEN_GEN11 }
	GCLK generator numbers. More...
enum	clock_mchp_pll_src_clock {   CLOCK_MCHP_PLL_SRC_GCLK0 , CLOCK_MCHP_PLL_SRC_GCLK1 , CLOCK_MCHP_PLL_SRC_GCLK2 , CLOCK_MCHP_PLL_SRC_GCLK3 ,   CLOCK_MCHP_PLL_SRC_GCLK4 , CLOCK_MCHP_PLL_SRC_GCLK5 , CLOCK_MCHP_PLL_SRC_GCLK6 , CLOCK_MCHP_PLL_SRC_GCLK7 ,   CLOCK_MCHP_PLL_SRC_GCLK8 , CLOCK_MCHP_PLL_SRC_GCLK9 , CLOCK_MCHP_PLL_SRC_GCLK10 , CLOCK_MCHP_PLL_SRC_GCLK11 ,   CLOCK_MCHP_PLL_SRC_XOSC , CLOCK_MCHP_PLL_SRC_DFLL48M , CLOCK_MCHP_PLL_SRC_MAX = CLOCK_MCHP_PLL_SRC_DFLL48M }
	PLL source clocks. More...
enum	clock_mchp_rtc_src_clock { CLOCK_MCHP_RTC_SRC_OSCULP1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP1K_Val , CLOCK_MCHP_RTC_SRC_OSCULP32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_ULP32K_Val , CLOCK_MCHP_RTC_SRC_XOSC1K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC1K_Val , CLOCK_MCHP_RTC_SRC_XOSC32K = OSC32KCTRL_CLKSELCTRL_RTCSEL_XOSC32K_Val }
	RTC source clocks. More...
enum	clock_mchp_gclk_src_clock {   CLOCK_MCHP_GCLK_SRC_XOSC , CLOCK_MCHP_GCLK_SRC_GCLKPIN , CLOCK_MCHP_GCLK_SRC_GCLKGEN1 , CLOCK_MCHP_GCLK_SRC_OSCULP32K ,   CLOCK_MCHP_GCLK_SRC_XOSC32K , CLOCK_MCHP_GCLK_SRC_DFLL48M , CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT0 , CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT1 ,   CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT2 , CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT3 , CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT4 , CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT5 ,   CLOCK_MCHP_GCLK_SRC_MAX = CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT5 }
	Gclk Generator source clocks. More...
enum	clock_mchp_mclk_cpu_div {   CLOCK_MCHP_MCLK_CPU_DIV_1 = 1 , CLOCK_MCHP_MCLK_CPU_DIV_2 = 2 , CLOCK_MCHP_MCLK_CPU_DIV_4 = 4 , CLOCK_MCHP_MCLK_CPU_DIV_8 = 8 ,   CLOCK_MCHP_MCLK_CPU_DIV_16 = 16 , CLOCK_MCHP_MCLK_CPU_DIV_32 = 32 , CLOCK_MCHP_MCLK_CPU_DIV_64 = 64 , CLOCK_MCHP_MCLK_CPU_DIV_128 = 128 }
	division ratio of mclk prescaler for CPU More...

Detailed Description

Clock control header file for Microchip pic32ck_sg_gc family.

This file provides clock driver interface definitions and structures for pic32ck_sg_gc family

Typedef Documentation

clock_mchp_rate_t

typedef uint32_t* clock_mchp_rate_t

clock rate datatype

Used for setting a clock rate

Enumeration Type Documentation

clock_mchp_gclk_src_clock

enum clock_mchp_gclk_src_clock

Gclk Generator source clocks.

Enumerator
CLOCK_MCHP_GCLK_SRC_XOSC
CLOCK_MCHP_GCLK_SRC_GCLKPIN
CLOCK_MCHP_GCLK_SRC_GCLKGEN1
CLOCK_MCHP_GCLK_SRC_OSCULP32K
CLOCK_MCHP_GCLK_SRC_XOSC32K
CLOCK_MCHP_GCLK_SRC_DFLL48M
CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT0
CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT1
CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT2
CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT3
CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT4
CLOCK_MCHP_GCLK_SRC_PLL0_CLKOUT5
CLOCK_MCHP_GCLK_SRC_MAX

clock_mchp_gclkgen

enum clock_mchp_gclkgen

GCLK generator numbers.

Enumerator
CLOCK_MCHP_GCLKGEN_GEN0
CLOCK_MCHP_GCLKGEN_GEN1
CLOCK_MCHP_GCLKGEN_GEN2
CLOCK_MCHP_GCLKGEN_GEN3
CLOCK_MCHP_GCLKGEN_GEN4
CLOCK_MCHP_GCLKGEN_GEN5
CLOCK_MCHP_GCLKGEN_GEN6
CLOCK_MCHP_GCLKGEN_GEN7
CLOCK_MCHP_GCLKGEN_GEN8
CLOCK_MCHP_GCLKGEN_GEN9
CLOCK_MCHP_GCLKGEN_GEN10
CLOCK_MCHP_GCLKGEN_GEN11

clock_mchp_mclk_cpu_div

enum clock_mchp_mclk_cpu_div

division ratio of mclk prescaler for CPU

Enumerator
CLOCK_MCHP_MCLK_CPU_DIV_1
CLOCK_MCHP_MCLK_CPU_DIV_2
CLOCK_MCHP_MCLK_CPU_DIV_4
CLOCK_MCHP_MCLK_CPU_DIV_8
CLOCK_MCHP_MCLK_CPU_DIV_16
CLOCK_MCHP_MCLK_CPU_DIV_32
CLOCK_MCHP_MCLK_CPU_DIV_64
CLOCK_MCHP_MCLK_CPU_DIV_128

clock_mchp_pll_src_clock

enum clock_mchp_pll_src_clock

PLL source clocks.

Enumerator
CLOCK_MCHP_PLL_SRC_GCLK0
CLOCK_MCHP_PLL_SRC_GCLK1
CLOCK_MCHP_PLL_SRC_GCLK2
CLOCK_MCHP_PLL_SRC_GCLK3
CLOCK_MCHP_PLL_SRC_GCLK4
CLOCK_MCHP_PLL_SRC_GCLK5
CLOCK_MCHP_PLL_SRC_GCLK6
CLOCK_MCHP_PLL_SRC_GCLK7
CLOCK_MCHP_PLL_SRC_GCLK8
CLOCK_MCHP_PLL_SRC_GCLK9
CLOCK_MCHP_PLL_SRC_GCLK10
CLOCK_MCHP_PLL_SRC_GCLK11
CLOCK_MCHP_PLL_SRC_XOSC
CLOCK_MCHP_PLL_SRC_DFLL48M
CLOCK_MCHP_PLL_SRC_MAX

clock_mchp_rtc_src_clock

enum clock_mchp_rtc_src_clock

RTC source clocks.

Enumerator
CLOCK_MCHP_RTC_SRC_OSCULP1K
CLOCK_MCHP_RTC_SRC_OSCULP32K
CLOCK_MCHP_RTC_SRC_XOSC1K
CLOCK_MCHP_RTC_SRC_XOSC32K