9#ifndef _TEST_ASM_INLINE_GCC_H
10#define _TEST_ASM_INLINE_GCC_H
15#error test_asm_inline_gcc.h goes only with GCC
18#if defined(CONFIG_X86)
21 __asm__ __volatile__ (
22 "xorl %%eax,%%eax;\n\t"
26 :
"%eax",
"%ebx",
"%ecx",
"%edx");
28#elif defined(CONFIG_CPU_ARM9) || \
29 defined(CONFIG_CPU_CORTEX_M) || \
30 defined(CONFIG_CPU_AARCH32_CORTEX_R) || \
31 defined(CONFIG_CPU_AARCH32_CORTEX_A) || \
32 defined(CONFIG_CPU_CORTEX_A) || \
33 defined(CONFIG_CPU_AARCH64_CORTEX_R)
38#elif defined(CONFIG_ARC)
39#define timestamp_serialize()
40#elif defined(CONFIG_ARCH_POSIX)
41#define timestamp_serialize()
42#elif defined(CONFIG_XTENSA)
43#define timestamp_serialize()
44#elif defined(CONFIG_RISCV)
45#define timestamp_serialize()
46#elif defined(CONFIG_SPARC)
47#define timestamp_serialize()
48#elif defined(CONFIG_MIPS)
49#define timestamp_serialize()
50#elif defined(CONFIG_RX)
51#define timestamp_serialize()
52#elif defined(CONFIG_OPENRISC)
53#define timestamp_serialize()
55#error implementation of timestamp_serialize() not provided for your CPU target
static ALWAYS_INLINE void barrier_isync_fence_full(void)
Full/sequentially-consistent instruction synchronization barrier.
Definition barrier.h:92
static void timestamp_serialize(void)
Definition test_asm_inline_other.h:15