microchip,pic32ck-sg-gc-gclkgen

Description

PIC32CK_SG_GC Generic clock generator

The Generic Clock controller (GCLK) features 12 Generic Clock Generators [11:0] that can
provide a wide range of clock frequencies.

Properties

Top level properties

These property descriptions apply to “microchip,pic32ck-sg-gc-gclkgen” nodes themselves. This page also describes child node properties in the following sections.

Properties not inherited from the base binding file.

(None)

Child node properties

Name

Type

Details

subsystem

int

Clock subsystem

This property is required.

gclkgen-en

int

A Generator is enabled by writing a '1' to the Generator Enable bit
in the Generator Control register
A Generator is disabled by writing a '0'

Default value: 1

Legal values: 0, 1

gclkgen-run-in-standby-en

int

Keep the Generator running in Standby as long as it is configured to output to a dedicated
GCLK_IOn pin. If output is not configured to a pin, this field has no effect and the
generator will only be running if a peripheral requires the clock.
0 - run in standby disable
1 - run in standby enable

Legal values: 0, 1

gclkgen-ext-input-frequency

int

The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO).

gclkgen-src

string

Generator source clock selection

Default value: pll0_0

Legal values: xosc, gclk-pin, gclk1, osculp32k, xosc32k, dfll48m, pll0_0, pll0_1, pll0_2, pll0_3, pll0_4, pll0_5

gclkgen-output-off-val

string

Output value of the corresponding pin, when the Generator is turned off or the output-en is
false, as long as the pin is not source.

Default value: logic-level-0

Legal values: logic-level-0, logic-level-1

gclkgen-input-frequency

int

External input clock frequency of the pin, when used as source. (0 - 200000000)

gclkgen-div-select

string

The Generator clock frequency equals the clock source frequency divided by div-factor
DIV_FACTOR_POWER: The Generator clock frequency equals the clock source frequency divided
by 2^(N+1), where N is the div-factor

Default value: div-factor

Legal values: div-factor, div-factor-power

gclkgen-div-factor

int

Represent a division value for the corresponding Generator. The actual division factor is
dependent on the state of div-select (gclk1 0 - 65535, others 0 - 255)

Default value: 1

gclkgen-duty-50-50-en

int

Improve the duty cycle of the Generator output to 50/50 for odd division factors

Legal values: 0, 1

gclkgen-out-clock-signal

int

0 - No Generator clock signal on pin GCLK_IO.
1 -The Generator clock signal is output on the corresponding GCLK_IO, unless
GCLK_IO is selected as a generator source in the GENCTRLn.SRC bit field.

Legal values: 0, 1