microchip,mcan-g1
Description
Microchip M_CAN FD Controller (Group 1)
Microchip M_CAN CAN FD controller
Unified binding for all Microchip MCUs using the Bosch M_CAN IP core
(ISO 11898-1:2015, CAN 2.0 part A/B, CAN FD).
Supported families:
- PIC32CK SG/GC series
Examples
can0: can@deadbeef {
compatible = "microchip,mcan-g1";
reg = <0xdeadbeef 0x100>;
interrupts = <143 0>;
clocks = <&mclkperiph CLOCK_MCHP_MCLKPERIPH_ID_CAN0_AHB>,
<&gclkperiph CLOCK_MCHP_GCLKPERIPH_ID_CAN0>;
clock-names = "mclk", "gclk";
bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
pinctrl-0 = <&can0_default>;
pinctrl-names = "default";
status = "disabled";
};
Properties
Top level properties
These property descriptions apply to “microchip,mcan-g1” nodes themselves. This page also describes child node properties in the following sections.
Properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
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Bosch M_CAN message RAM configuration. The cells in the array have the following format:
<offset std-filter-elements ext-filter-elements rx-fifo0-elements rx-fifo1-elements
rx-buffer-elements tx-event-fifo-elements tx-buffer-elements>
The 'offset' is an address offset of the message RAM where the following elements start
from. This is normally set to 0x0 when using a non-shared message RAM. The remaining cells
specify how many elements are allocated for each filter type/FIFO/buffer.
The Bosch M_CAN IP supports the following elements:
11-bit Filter 0-128 elements / 0-128 words
29-bit Filter 0-64 elements / 0-128 words
Rx FIFO 0 0-64 elements / 0-1152 words
Rx FIFO 1 0-64 elements / 0-1152 words
Rx Buffers 0-64 elements / 0-1152 words
Tx Event FIFO 0-32 elements / 0-64 words
Tx Buffers 0-32 elements / 0-576 words
This property is required. |
|
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Configures the internal timestamp counter time unit in multiples of CAN bit times. Valid range
is 1 to 16. The default value is a prescaler of 1, such that the time unit equals one CAN bit
time.
Default value: Legal values: |
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Initial data phase bitrate in bit/s. If this is unset, the initial data phase bitrate is set
to CONFIG_CAN_DEFAULT_BITRATE_DATA.
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Initial data phase sample point in per mille (e.g. 875 equals 87.5%).
If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for
bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other
bitrates.
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Initial bitrate in bit/s. If this is unset, the initial bitrate is set to
CONFIG_CAN_DEFAULT_BITRATE.
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Initial sample point in per mille (e.g. 875 equals 87.5%).
If this is unset (or if it is set to 0), the initial sample point will default to 75.0% for
bitrates over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all other
bitrates.
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Actively controlled CAN transceiver.
Example:
transceiver0: can-phy0 {
compatible = "nxp,tja1040", "can-transceiver-gpio";
standby-gpios = <gpioa 0 GPIO_ACTIVE_HIGH>;
max-bitrate = <1000000>;
#phy-cells = <0>;
};
&can0 {
status = "okay";
phys = <&transceiver0>;
};
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Pin configuration/s for the first state. Content is specific to the
selected pin controller driver implementation.
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Pin configuration/s for the second state. See pinctrl-0.
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Pin configuration/s for the third state. See pinctrl-0.
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Pin configuration/s for the fourth state. See pinctrl-0.
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Pin configuration/s for the fifth state. See pinctrl-0.
|
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Names for the provided states. The number of names needs to match the
number of states.
|
Deprecated properties not inherited from the base binding file.
Name |
Type |
Details |
|---|---|---|
|
|
Deprecated. This property has been renamed to bitrate-data.
Initial data phase bitrate in bit/s. If this is unset, the initial data phase bitrate is set
to CONFIG_CAN_DEFAULT_BITRATE_DATA.
|
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Deprecated. This property has been renamed to bitrate.
Initial bitrate in bit/s. If this is unset, the initial bitrate is set to
CONFIG_CAN_DEFAULT_BITRATE.
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Properties inherited from the base binding file, which defines common properties that may be set on many nodes. Not all of these may apply to the “microchip,mcan-g1” compatible.
Name |
Type |
Details |
|---|---|---|
|
|
Information used to address the device. The value is specific to
the device (i.e. is different depending on the compatible
property).
The "reg" property is typically a sequence of (address, length) pairs.
Each pair is called a "register block". Values are
conventionally written in hex.
For details, see "2.3.6 reg" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
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Information about interrupts generated by the device, encoded as an array
of one or more interrupt specifiers. The format of the data in this property
varies by where the device appears in the interrupt tree. Devices with the same
"interrupt-parent" will use the same format in their interrupts properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
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Phandles to the clock controllers. Must provide two clocks:
1. MCLK (AHB bus clock) - required for bus access
2. GCLK (peripheral clock) - core clock for CAN timing
This property is required. |
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Clock names for the CAN peripheral. Must include:
- "mclk" for the AHB bus clock (MCLK peripheral)
- "gclk" for the peripheral clock (GCLK peripheral)
This property is required. |
|
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Indicates the operational status of the hardware or other
resource that the node represents. In particular:
- "okay" means the resource is operational and, for example,
can be used by device drivers
- "disabled" means the resource is not operational and the system
should treat it as if it is not present
For details, see "2.3.4 status" in Devicetree Specification v0.4.
Legal values: See Important properties for more information. |
|
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This property is a list of strings that essentially define what
type of hardware or other resource this devicetree node
represents. Each device driver checks for specific compatible
property values to find the devicetree nodes that represent
resources that the driver should manage.
The recommended format is "vendor,device", The "vendor" part is
an abbreviated name of the vendor. The "device" is usually from
the datasheet.
The compatible property can have multiple values, ordered from
most- to least-specific. Having additional values is useful when the
device is a specific instance of a more general family, to allow the
system to match the most specific driver available.
For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
This property is required. See Important properties for more information. |
|
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Optional names given to each register block in the "reg" property.
For example:
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
uart@1000 {
reg = <0x1000 0x2000>, <0x3000 0x4000>;
reg-names = "foo", "bar";
};
};
};
The uart@1000 node has two register blocks:
- one with base address 0x1000, size 0x2000, and name "foo"
- another with base address 0x3000, size 0x4000, and name "bar"
|
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Extended interrupt specifier for device, used as an alternative to
the "interrupts" property.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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Optional names given to each interrupt generated by a device.
The interrupts themselves are defined in either "interrupts" or
"interrupts-extended" properties.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
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If present, this refers to the node which handles interrupts generated
by this device.
For details, see "2.4 Interrupts and Interrupt Mapping" in
Devicetree Specification v0.4.
|
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Human readable string describing the device. Use of this property is
deprecated except as needed on a case-by-case basis.
For details, see "4.1.2 Miscellaneous Properties" in Devicetree
Specification v0.4.
See Important properties for more information. |
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This property encodes the number of <u32> cells used by address fields
in "reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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This property encodes the number of <u32> cells used by size fields in
"reg" properties in this node's children.
For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
Specification v0.4.
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DMA channel specifiers relevant to the device.
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Optional names given to the DMA channel specifiers in the "dmas" property.
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IO channel specifiers relevant to the device.
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Optional names given to the IO channel specifiers in the "io-channels" property.
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Mailbox / IPM channel specifiers relevant to the device.
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Optional names given to the mbox specifiers in the "mboxes" property.
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Power domain specifiers relevant to the device.
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Optional names given to the power domain specifiers in the "power-domains" property.
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Number of cells in power-domains property
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HW spinlock id relevant to the device.
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Optional names given to the hwlock specifiers in the "hwlocks" property.
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Do not initialize device automatically on boot. Device should be manually
initialized using device_init().
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Property to identify that a device can be used as wake up source.
When this property is provided a specific flag is set into the
device that tells the system that the device is capable of
wake up the system.
Wake up capable devices are disabled (interruptions will not wake up
the system) by default but they can be enabled at runtime if necessary.
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Automatically configure the device for runtime power management after the
init function runs.
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List of power states that will disable this device power.
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Child node properties
Name |
Type |
Details |
|---|---|---|
|
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The minimum bitrate supported by the CAN transceiver in bits/s.
|
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The maximum bitrate supported by the CAN transceiver in bits/s.
This property is required. |